1. Field of the Invention
The present invention relates to a circuit and associated method for emulating the output of a serial pseudo-random generator (PRG) or scrambler by a parallel implementation comprising a plurality of outputs which represent successive serial outputs of the serial PRG. The invention has particular use in telecommunications, where high speed data streams are combined with a serial PRG so as to insure proper clocking and for potential security of the data stream. Due to the high-speed nature of such telecommunication data, serial PRG's cannot be implemented using complimentary metal oxide silicon (CMOS) circuitry. Thus there is a need for emulating the serial PRG so that the clock rate of the circuitry is within the operating frequency of CMOS circuitry.
2. Description of the Related Art
Since the adoption of the synchronous optical network specification (SONET), a standard has been set for high-speed digital telecommunications (see American National Standards Institute, Inc. "Digital Hierarchy Optical Interface Rates and Formats Specification" standard TI.105--1988). Typically, such digital telecommunications combine a pseudo-random serial scrambling signal with the data stream so as to minimize the possibility of loss of clock signal which might otherwise result if the data stream comprised a large number of adjacent 0's or 1's. However, due to the fact that the serial data stream may operate at 155 megabits per second or higher, the serial PRG has to be implemented using high speed fabrication techniques, such as discrete emitter coupled logic (ECL) circuitry, ECL application specific integrated circuitry (ECL ASIC) or gallium arsenide (GaAs) circuitry, rather than the preferable CMOS circuitry which is less expensive to fabricate and operates at lower power than corresponding ECL or gallium arsenide circuitry. The additional fabrication costs and power requirements of ECL and GaAs circuitry also require more printed circuit board area in order to dissipate the additional heat, again making CMOS circuitry and especially CMOS application specific integrated circuitry (CMOS ASIC) preferable.
Due to the fact that CMOS circuitry cannot typically operate at clock speeds greater than 50 megahertz, it is necessary that a technique be used to effectively reduce the clock frequency of the serial pseudo-random generator. The present invention describes such a technique and circuit which is operable for any serial PRG generating polynomial, as well as for any size parallel output word larger than the length of the equivalent serial shift register, representing the successive outputs from the serial PRG.
In this manner, relatively low cost, low power consumption CMOS circuitry can be used to fabricate a parallel PRG which emulates the output of a serial PRG.